MC2 automates the design process for standard and embedded memories. MC2 also provides a platform for seamless migration to new processes.
- Creates Various Views
- Physical Views - GDSII, LEF; Logical Views - SPICE, Verilog
- Timing Models - Verilog, Synopsys, VHDL, ALF
- Data sheet
- Any Proprietary Model Based on Given Template
- Enables Automatic Tiling and Netlisting
- Generates Power Ring/Power Mesh
- Has an integrated and programmable BIST engine
- Provides a Memory Design Framework
- Allows Via Programming, Decoder Building, ROM Programming
- Generates Internal Routes
- Contains a delay and power characterization module
- Provides GDS Import for Legacy Memory Designs
- Encrypts Memory Architecture files for Secure Distribution
- Automates interpolation and derating for delay/power numbers for all sizes
