矽智財

Interface IP in production

Gigabit Ethernet
Gigabit Ethernet PHY (in production)

  • Integrated 10/100/1000Mbps Transceiver
  • Compliant with IEEE 802.3, IEEE 802.3u, and IEEE 802.3ab
  • Support IEEE P802.3az D3.2 Energy Efficient Ethernet
  • Support GMII/RGMII interface to MAC
  • Silicon proven and mass production IP records

USB 2.0 PHY

  • Compliance with USB 2.0 electrical specification
  • Support USB High-Speed and Full-Speed Operation
  • Compliance with USB Mass Storage Class, Bulk-Only Transport Specification
  • Support 12MHz external crystal
  • Silicon proven and mass production IP records

USB 3.0 PHY

  • Complies with USB 3.0 Specification, USB Mass Storage Class, Bulk-Only Transport Specification
  • Supports USB Super-Speed/High-Speed/Full-Speed Operation
  • Supports USB2.0/USB3.0 power saving mode
  • Supports 30MHz external crystal
  • Silicon proven and mass production IP records

USB 3.1 PHY

  • Complies with USB 3.1 Specification, USB Mass Storage Class, Bulk-Only Transport Specification
  • Supports USB Super-Speed/High-Speed/Full-Speed Operation
  • Supports USB2.0/USB3.1 power saving mode
  • Supports 30MHz external crystal
  • Silicon proven and mass production IP records
PCIe gen3 PHY

  • Compliant with PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
  • Supports x2 Lanes
  • Supports PIPE 4.0 interface
  • Support for low power modes for PCIe — L0s, L1, L1.1, L1.2, and L2
  • Clock data recovery with greater than +/- 300 PPM
  • Silicon proven and mass production IP records
SATA 2 PHY

  • Compliant with Serial ATA International Organization: Serial ATA Revision 2.6
  • Compliant with SATA 2.6 specification, Gen1i/m(1.5Gbps), Gen2i/m(3.0Gbps)
  • Support SATA II Asynchronous Signal Recovery (Hot Plug) feature
  • Support SATA 30MHz or 40MHz external crystal
  • Silicon proven and mass production IP records

SATA 3 PHY

  • Compliant with Serial ATA International Organization: Serial ATA Revision 3.1
  • Compliant with 6G PHY Working Group Specification Revisions for Gen3i(6Gbps)
  • Compliant with SATA 2.6 specification, Gen1i/m(1.5Gbps), Gen2i/m(3.0Gbps)
  • Supports 30MHz external crystal
  • Silicon proven and mass production IP records
DDR3 PHY

  • DFI 3.1-like interface
  • Support for DDR3 and LPDDR3
  • Data rate up to 1400~1600 Mbps
  • Support for multiple DRAM widths(x16, x32)
  • Support for up to 2 x DRAMs
  • PHY-Controller interface runs in 1:1 or 1:2 mode
  • Silicon proven and mass production IP records
MIPI M-PHY

  • Supports MIPI Alliance Specification for M-PHY Version 3.0
  • Supports HS-MODE; HS-G1, HS-G2, HS-G3
  • Supports Type-I LS-MODE; PWM-G0, PWM-G1 and PWM-G2 to G7
  • Supports the following standards: CSI-3, DSI-2, Uniport-M(UniPro 1.41) LLI and JC-64.1 UFS
  • 1-6 Gbps data rate in HS mode
  • 01-576 Mbps data rate in LS mode
  • Silicon proven

MIPI D-PHY

  • Consists of 1 Clock lane and up to 4 Data lanes
  • Supports MIPI Standard 1.1 for D-PHY
  • Supports both high speed and low-power mode
  • 80Mbps to 1.5Gbps data rate in high speed mode
  • 10Mbps data rate in low-power mode
  • Can be configured as a MIPI Master or MIPI Slave optimized for camera interface (CSI-2) and display (DSI) applications
  • Silicon proven


MIPI C/D-PHY Combo

  • Silicon proven
  • Please contact sales for more information

High-end Analog IP design

ADC/DAC
ADC – Silicon proven

  • 10-bit 200Msps Pipelined ADC
  • 11-bit 100Msps Pipelined ADC
  • 12-bit 160Msps Pipelined ADC
  • 14-bit 25Msps Pipelined ADC
  • 12-bit 5Msps SAR ADC for automotive

DAC – Silicon proven

  • 12-bit 320Msps Current Steering DAC
  • 14-bit 1Msps Low Power High Resolution Rail to Rail DAC
SerDes
SerDes

  • 1.5Gbps/3Gbps/6Gbps SerDes
  • 2.5Gbps/5Gbps/8Gbps SerDes
  • 1.25Gbps SGMII SerDes
Clock
Clock

  • PLL, DLL, SSCG custom design
LVDS
LVDS

  • LVDS Transmitter
  • LVDS Receiver
LDO
LDO Regulator

  • LDO Regulator custom design